In a display device such as an active matrix liquid crystal display device, there are formed a plurality of data signal lines (also called “source lines”), a plurality of scanning signal lines (also called “gate lines”) across the plurality of data signal lines, and a plurality of pixel formation portions disposed in a matrix pattern along the plurality of data signal lines and the plurality of scanning signal lines, on a display section such as a liquid crystal panel. Among these active matrix display devices, there are those which make use of dot sequential driving method, or SSD (Source Shared Driving) method. In the SSD method, a plurality of data signal lines in the display section are grouped into a plurality of data signal line groups each consisting of two or more predetermined number of data signal lines. The predetermined number of data signal lines in each group are supplied with analog video signals in a time-sharing fashion.
In cases where an active matrix display device makes use of the dot sequential driving method, SSD method, etc., each data signal line is supplied with an analog video signal via an ON-state analog switch; and thereafter, the analog switch's control signal level is changed to turn OFF the analog switch, whereby a voltage of the analog video signal is held in the data signal line. While the analog video signal voltage is held in each data signal line as described, one of the above-described plurality of scanning signal lines is activated (selected), whereby a voltage in the data signal line is written as a pixel data to a pixel formation portion connected to the activated scanning signal line.
(B) of FIG. 6 is a circuit diagram which shows a configuration of a portion (hereinafter called “unit sample-and-holding circuit”) corresponding to one data signal line SLk (hereinafter called “focused data signal line SLk”) of a sample-and-holding circuit that works in sampling analog video signals and. having each data signal line SLi (i−1 through N) hold the signal in a display device as described above (see Patent Documents 1 and 2). The unit sample-and-holding circuit includes an N channel type field effect transistor (hereinafter abbreviated as “Nch transistor”) SWk serving as the analog switch; an inverter IV for making logical inversion of a control signal Sck of this analog switch; a correction capacitance element Cc which has its one end connected to the focused data signal line SL and another end connected to an output terminal of the inverter IV; and a parasitic capacitance Cgd formed between a gate terminal of the Nch transistor SWk and one of conduction terminals connected to the focused data signal line SL. The other conduction terminal of the Nch transistor SWk is supplied with an analog video signal Sv1, whereas the gate terminal of the Nch transistor SWk is supplied with the earlier-described control signal Sck. These Nch transistor SWk (including the parasitic capacitance Cgd), correction capacitance element Cc and inverter IV constitute a sampling circuit of the analog video signal Sv1. The sampling circuit and the focused data signal line's capacitance (total capacitance formed by the focused data signal line SLk and other electrodes) Csl constitute the above-mentioned unit sample-and-holding circuit.
In the sampling circuit, when the analog switch SWk is turned ON, the control signal Sck provided by a predetermined ON voltage (a HIGH level voltage (hereinafter called “H level voltage VH”) in cases where the analog switch is provided by an Nch transistor) is applied to the gate terminal of the Nch transistor SWk, whereas when the analog switch is turned OFF, the control signal Sck provided by a predetermined OFF voltage (a LOW level voltage (hereinafter called “L level voltage VL”) in cases where the analog switch is provided by an Nch transistor) is applied to the gate terminal of the Nch transistor SWk.
When turning OFF the Nch transistor SWk after applying an analog video signal Sv to the focused data signal line SLk via the Nch transistor SWk which works as the analog switch, the voltage of the control signal Sck starts from the ON voltage which is represented by the H level voltage VH toward the OFF voltage which is represented by the L level voltage VL; and when a potential difference between the gate terminal and the source terminal in the Nch transistor SWk reaches a threshold voltage Vth of the transistor SWk, namely, when the voltage of the control signal Sck becomes equal to a sum of a voltage Vv1 of the video signal Sv1 and the threshold voltage Vth, or a voltage Vv1+Vth (hereinafter this voltage Vv1+Vth will be called “OFF transition voltage Voff”), the transistor SWk assumes an OFF state. Thereafter, the voltage of the control signal Sck (hereinafter called “control voltage Vg”) falls from the OFF transition voltage Voff to the L level voltage VL. This change in the control voltage Vg, from the OFF transition voltage Voff to the L level voltage VL, lowers a voltage of the focused data signal line SLk (hereinafter called “data signal line voltage”) Vsl via the parasitic capacitance Cgd. Therefore, the sampling circuit in (B) of FIG. 6 is configured to cause the inverter IV to generate an inverted signal Sr by making a logical inversion of the control signal Sck and to apply this inverted signal Sr to the focused data signal line SLk via the correction capacitance element Cc. This reduces the drop in the data signal line voltage Vsl caused by the parasitic capacitance Cgd.